Through vertical interconnect access (via) is a vertical electrical connection passing completely through a silicon wafer or interposer. Through-silicon via (TSV) contact demonstrates a high performance technique used to create smaller packages and integrated circuits. This technique improves physical scaling limitations while delivering greater performance and functionality. Redistribution layer (RDL) or conductive lines disposed over the silicon wafer or interposer require alignment with underlying TSV contacts. Conventional manufacturing process employs an extra zero-mark layer to assist in the alignment of the conductive lines and underlying TSV contacts. However, conventional processes may result in reliability issues, such as wafer dicing crack concern, and increases the manufacturing costs.
From the foregoing discussion, it is desirable to provide simplified, cost efficient and improved techniques for alignment of RDL or conductive lines with underlying TSV contacts.